Two Bit Error Rate Test (BERT) cores are available from ESD
Serial mode Bit Error Rate Test Core operates on one bit per clock and is configurable for 5 different patterns. Suitable for low bit rate testing such as T1 or DS3.Parallel 8 bit Bit Error Rate Test Core operates on 8 bits per clock and is configurable for 2 different patterns. Suitable for medium bit rate testing such as OC3 or OC12.
Electronic Systems Development - Email: dpd@esysdev.com